[PATCH] D71701: [AArch64] Peephole optimization. Merge AND and TST instructions

Pavel Kosov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 29 05:13:35 PST 2020


kpdev42 updated this revision to Diff 241119.
kpdev42 added a comment.

Update patch: move all changes to `AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI)` as it was planned.
But I do not know if it is a finally version, because as I see from the discussion - moving this functionality to ISel is more preferable.
So, do I need to create another patch with ISel implementation (I mean - create another differential revision), or it is better to change this patch?

In D71701#1846226 <https://reviews.llvm.org/D71701#1846226>, @craig.topper wrote:

> I assume the TST started as an ISD::SETCC and ISD::AND then the AArch64ISD::ANDS was generated from that. While still leaving the ISD::AND around for the use that wasn't the ISD::SETCC. On X86 when we create X86ISD::AND (which is our flag setting opcode) we replace all other uses of the ISD::AND with the data output of the X86ISD::AND. See EmitTest in X86ISelLowering. Maybe something like that would work here?


Thank you! I definitely will take a look at it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71701/new/

https://reviews.llvm.org/D71701

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/test/CodeGen/AArch64/peephole-and-tst.ll

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