[PATCH] D71701: [AArch64] Peephole optimization. Merge AND and TST instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I assume the TST started as an ISD::SETCC and ISD::AND then the AArch64ISD::ANDS was generated from that. While still leaving the ISD::AND around for the use that wasn't the ISD::SETCC. On X86 when we create X86ISD::AND (which is our flag setting opcode) we replace all other uses of the ISD::AND with the data output of the X86ISD::AND. See EmitTest in X86ISelLowering. Maybe something like that would work here?


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https://reviews.llvm.org/D71701