[PATCH] D73582: [AMDGPU] override isHighLatencyDef
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 28 14:25:29 PST 2020
rampitec created this revision.
rampitec added reviewers: foad, dstuttard, arsenm.
Herald added subscribers: kerbowa, javed.absar, hiraditya, t-tye, tpr, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, MatzeB.
Herald added a project: LLVM.
SIMachineScheduler uses isHighLatencyInstruction with the same
sematincs, but TargetInstrInfo has virtual isHighLatencyDef
method, so override it instead.
Added FLAT to the list of high latency opcodes and a check for
mayLoad since stores are not technically high latency in terms
of data dependency.
This change did not produce any visible impact on our tests.
https://reviews.llvm.org/D73582
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
Index: llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -1955,7 +1955,7 @@
if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
TRI))
LowLatencyOffset[i] = OffLatReg;
- } else if (SITII->isHighLatencyInstruction(*SU->getInstr()))
+ } else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))
IsHighLatencySU[i] = 1;
}
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -931,7 +931,7 @@
uint64_t getScratchRsrcWords23() const;
bool isLowLatencyInstruction(const MachineInstr &MI) const;
- bool isHighLatencyInstruction(const MachineInstr &MI) const;
+ bool isHighLatencyDef(int Opc) const override;
/// Return the descriptor of the target-specific machine instruction
/// that corresponds to the specified pseudo or native opcode.
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6021,10 +6021,9 @@
return isSMRD(Opc);
}
-bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {
- unsigned Opc = MI.getOpcode();
-
- return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc);
+bool SIInstrInfo::isHighLatencyDef(int Opc) const {
+ return get(Opc).mayLoad() &&
+ (isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc) || isFLAT(Opc));
}
unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
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