[PATCH] D73488: [mlir] add lowering from affine.min to std
River Riddle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 27 13:48:17 PST 2020
rriddle added inline comments.
================
Comment at: mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp:274
+// Emit instructions that correspond to computing the minimum value amoung the
+// values of a (potentially) multi-output affine map applied to `operands`.
----------------
These should be ///
================
Comment at: mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp:279
+ if (auto values =
+ expandAffineMap(builder, loc, map, llvm::to_vector<4>(operands)))
+ return buildMinMaxReductionSeq(loc, CmpIPredicate::slt, *values, builder);
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Can we just change expandAffineMap to use ValueRange instead?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D73488/new/
https://reviews.llvm.org/D73488
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