Author: Maheaha Shivamallappa
Date: 2020-01-26T14:09:31+05:30
New Revision: 66f93071cdfc26edfbc5f4efe19a56fcf2d05594
URL: https://github.com/llvm/llvm-project/commit/66f93071cdfc26edfbc5f4efe19a56fcf2d05594
DIFF: https://github.com/llvm/llvm-project/commit/66f93071cdfc26edfbc5f4efe19a56fcf2d05594.diff
LOG: AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics.
Summary:
A minor code clean-up around ISel for intrinsic llvm.amdgcn.end.cf()
Reviewers: arsenm, mshivama
Reviewed By: arsenm
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73358
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 6ca7e6cb04fd..ce47e56da02a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1027,6 +1027,21 @@ AMDGPUInstructionSelector::splitBufferOffsets(MachineIRBuilder &B,
return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset);
}
+bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
+ // FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
+ // SelectionDAG uses for wave32 vs wave64.
+ MachineBasicBlock *BB = MI.getParent();
+ BuildMI(*BB, &MI, MI.getDebugLoc(), TII.get(AMDGPU::SI_END_CF))
+ .add(MI.getOperand(1));
+
+ Register Reg = MI.getOperand(1).getReg();
+ MI.eraseFromParent();
+
+ if (!MRI->getRegClassOrNull(Reg))
+ MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
+ return true;
+}
+
bool AMDGPUInstructionSelector::selectStoreIntrinsic(MachineInstr &MI,
bool IsFormat) const {
MachineIRBuilder B(MI);
@@ -1306,23 +1321,10 @@ bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI,
bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &I) const {
- MachineBasicBlock *BB = I.getParent();
unsigned IntrinsicID = I.getIntrinsicID();
switch (IntrinsicID) {
- case Intrinsic::amdgcn_end_cf: {
- // FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
- // SelectionDAG uses for wave32 vs wave64.
- BuildMI(*BB, &I, I.getDebugLoc(),
- TII.get(AMDGPU::SI_END_CF))
- .add(I.getOperand(1));
-
- Register Reg = I.getOperand(1).getReg();
- I.eraseFromParent();
-
- if (!MRI->getRegClassOrNull(Reg))
- MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
- return true;
- }
+ case Intrinsic::amdgcn_end_cf:
+ return selectEndCfIntrinsic(I);
case Intrinsic::amdgcn_raw_buffer_store:
return selectStoreIntrinsic(I, false);
case Intrinsic::amdgcn_raw_buffer_store_format:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index 8d7827bfbc5f..d7dc8de3677d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -103,6 +103,7 @@ class AMDGPUInstructionSelector : public InstructionSelector {
std::tuple<Register, unsigned, unsigned>
splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
+ bool selectEndCfIntrinsic(MachineInstr &MI) const;
bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;