[PATCH] D73276: [VE] aligned load/store isel patterns
Simon Moll via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 24 01:09:38 PST 2020
simoll updated this revision to Diff 240117.
simoll marked 4 inline comments as done.
simoll added a comment.
More mature `SelectADDRri` implementation..
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D73276/new/
https://reviews.llvm.org/D73276
Files:
llvm/lib/Target/VE/VEISelDAGToDAG.cpp
llvm/lib/Target/VE/VEInstrInfo.td
llvm/test/CodeGen/VE/load.ll
llvm/test/CodeGen/VE/store.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D73276.240117.patch
Type: text/x-patch
Size: 16963 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200124/efc69afd/attachment.bin>
More information about the llvm-commits
mailing list