[PATCH] D73276: [VE] aligned load/store isel patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/VE/VEISelDAGToDAG.cpp:59
+bool VEDAGToDAGISel::SelectADDRri(SDValue Addr,
+                                     SDValue &Base, SDValue &Offset) {
+  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
----------------
Indentation


================
Comment at: llvm/lib/Target/VE/VEISelDAGToDAG.cpp:62
+    Base = CurDAG->getTargetFrameIndex(
+        FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
+    Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
----------------
This can reuse the existing type


================
Comment at: llvm/lib/Target/VE/VEISelDAGToDAG.cpp:71-72
+
+  if (Addr.getOpcode() == ISD::ADD) {
+    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+      if (isInt<13>(CN->getSExtValue())) {
----------------
Should use isBaseWithConstantOffset


================
Comment at: llvm/lib/Target/VE/VEISelDAGToDAG.cpp:78
+          Base = CurDAG->getTargetFrameIndex(
+              FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
+        } else {
----------------
Reuse the type


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D73276/new/

https://reviews.llvm.org/D73276