[PATCH] D71293: AMDGPU: Generate the correct sequence of code for FDIV32 when correctly-rounded-divide-sqrt is set
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 23 07:43:15 PST 2020
arsenm added inline comments.
================
Comment at: llvm/test/CodeGen/AMDGPU/fdiv.f16.ll:253
+
+!0 = !{float 2.500000e+00}
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arsenm wrote:
> I don't know what ulp the f16 rcp instruction provides. This test change looks incomplete if there isn't already a case without !fpmath
I found a document stating this provides "~0.5ulp", so I guess check that value for f16?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D71293/new/
https://reviews.llvm.org/D71293
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