[PATCH] D73247: AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32

Wed Jan 22 18:18:04 PST 2020

arsenm created this revision.
arsenm added reviewers: nhaehnle, kerbowa, rampitec, alex-t.
Herald added subscribers: Petar.Avramovic, jfb, hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
arsenm added a parent revision: D72627: AMDGPU/GlobalISel: Only map VOP operands to VGPRs.

The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.

I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction,
which will trivially them. However, it's possible to still have hand
written MIR (or erroneously transforms) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
restriction.

It might be worth triggering a DAG fallback on verifier error.

https://reviews.llvm.org/D73247

Files:
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D73247.239758.patch
Type: text/x-patch
Size: 41235 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200123/ca070198/attachment.bin>