[PATCH] D71293: AMDGPU: Generate the correct sequence of code for FDIV32 when correctly-rounded-divide-sqrt is set

[Changpeng Fang via Phabricator via llvm-commits]

cfang updated this revision to Diff 239724.
cfang marked an inline comment as done.
cfang added a comment.

update based on feedback.

1. Using arcp && (( no denormals && fpmath>=2.5) || afn)
2. update arcp related LIT tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71293/new/

https://reviews.llvm.org/D71293

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
  llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
  llvm/test/CodeGen/AMDGPU/fdiv.ll
  llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
  llvm/test/CodeGen/AMDGPU/fneg-combines.ll
  llvm/test/CodeGen/AMDGPU/known-never-snan.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
  llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
  llvm/test/CodeGen/AMDGPU/rsq.ll

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