[llvm] d6f4cfd - [llvm-exegesis] Add support for AVX512 explicit rounding operands.

[Clement Courbet via llvm-commits]

Author: Clement Courbet
Date: 2020-01-21T11:50:17+01:00
New Revision: d6f4cfdbd7923bae74d4a45f276f3b7f3e053f39

URL: https://github.com/llvm/llvm-project/commit/d6f4cfdbd7923bae74d4a45f276f3b7f3e053f39
DIFF: https://github.com/llvm/llvm-project/commit/d6f4cfdbd7923bae74d4a45f276f3b7f3e053f39.diff

LOG: [llvm-exegesis] Add support for AVX512 explicit rounding operands.

Reviewers: gchatelet

Subscribers: tschuett, mstojanovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73083

Added: 
    

Modified: 
    llvm/tools/llvm-exegesis/lib/X86/Target.cpp
    llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

Removed: 
    


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diff  --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
index d2da6c235eab..47b14f2e7c19 100644
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -636,6 +636,10 @@ void ExegesisX86Target::randomizeMCOperand(
 
   const Operand &Op = Instr.getPrimaryOperand(Var);
   switch (Op.getExplicitOperandInfo().OperandType) {
+  case X86::OperandType::OPERAND_ROUNDING_CONTROL:
+    AssignedValue =
+        MCOperand::createImm(randomIndex(X86::STATIC_ROUNDING::NO_EXC));
+    break;
   case X86::OperandType::OPERAND_COND_CODE:
     AssignedValue =
         MCOperand::createImm(randomIndex(X86::CondCode::LAST_VALID_COND));

diff  --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
index 5ad49927f6b5..808ea34e7437 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -198,6 +198,24 @@ TEST_F(SerialSnippetGeneratorTest, LAHF) {
   }
 }
 
+TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
+  // - VCVTUSI642SDZrrb_Int
+  // - Op0 Explicit Def RegClass(VR128X)
+  // - Op1 Explicit Use RegClass(VR128X)
+  // - Op2 Explicit Use STATIC_ROUNDING
+  // - Op2 Explicit Use RegClass(GR64)
+  // - Op4 Implicit Use Reg(MXSCR)
+  const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
+  const Instruction &Instr = State.getIC().getInstr(Opcode);
+  auto Configs =
+      Generator.generateConfigurations(Instr, State.getRATC().emptyRegisters());
+  ASSERT_FALSE(Configs.takeError());
+  ASSERT_THAT(*Configs, SizeIs(1));
+  const BenchmarkCode &BC = (*Configs)[0];
+  ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
+  ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
+}
+
 TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) {
   // - BNDCL32rr
   // - Op0 Explicit Use RegClass(BNDR)