[llvm] a672f57 - Regenerate rotated uxt tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 21 02:40:35 PST 2020
Author: Simon Pilgrim
Date: 2020-01-21T10:40:17Z
New Revision: a672f579a2f66dbfa72799dec8ac52858b9a0f99
URL: https://github.com/llvm/llvm-project/commit/a672f579a2f66dbfa72799dec8ac52858b9a0f99
DIFF: https://github.com/llvm/llvm-project/commit/a672f579a2f66dbfa72799dec8ac52858b9a0f99.diff
LOG: Regenerate rotated uxt tests
Added:
Modified:
llvm/test/CodeGen/ARM/uxt_rot.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/uxt_rot.ll b/llvm/test/CodeGen/ARM/uxt_rot.ll
index 472851362c69..15ea34a3d224 100644
--- a/llvm/test/CodeGen/ARM/uxt_rot.ll
+++ b/llvm/test/CodeGen/ARM/uxt_rot.ll
@@ -1,18 +1,21 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefix=CHECK-V6
-; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s --check-prefix=CHECK-V7
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6 | FileCheck %s --check-prefixes=CHECK,CHECK-V6
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v7 | FileCheck %s --check-prefixes=CHECK,CHECK-V7
define zeroext i8 @test1(i32 %A.u) {
- ; CHECK-LABEL: test1
- ; CHECK-V6: uxtb
- ; CHECK-V7: uxtb
+; CHECK-LABEL: test1:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: bx lr
%B.u = trunc i32 %A.u to i8
ret i8 %B.u
}
define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
- ; CHECK-LABEL: test2
- ; CHECK-V6: uxtab r0, r0, r1
- ; CHECK-V7: uxtab r0, r0, r1
+; CHECK-LABEL: test2:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtab r0, r0, r1
+; CHECK-NEXT: bx lr
%C.u = trunc i32 %B.u to i8
%D.u = zext i8 %C.u to i32
%E.u = add i32 %A.u, %D.u
@@ -20,9 +23,16 @@ define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
}
define zeroext i32 @test3(i32 %A.u) {
- ; CHECK-LABEL: test3
- ; CHECK-V6-NOT: ubfx
- ; CHECK-V7: ubfx r0, r0, #8, #16
+; CHECK-V6-LABEL: test3:
+; CHECK-V6: @ %bb.0:
+; CHECK-V6-NEXT: lsr r0, r0, #8
+; CHECK-V6-NEXT: uxth r0, r0
+; CHECK-V6-NEXT: bx lr
+;
+; CHECK-V7-LABEL: test3:
+; CHECK-V7: @ %bb.0:
+; CHECK-V7-NEXT: ubfx r0, r0, #8, #16
+; CHECK-V7-NEXT: bx lr
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u
@@ -32,9 +42,16 @@ define zeroext i32 @test3(i32 %A.u) {
}
define zeroext i32 @test4(i32 %A.u) {
- ; CHECK-LABEL: test4
- ; CHECK-V6-NOT: ubfx
- ; CHECK-V7: ubfx r0, r0, #8, #8
+; CHECK-V6-LABEL: test4:
+; CHECK-V6: @ %bb.0:
+; CHECK-V6-NEXT: lsr r0, r0, #8
+; CHECK-V6-NEXT: uxtb r0, r0
+; CHECK-V6-NEXT: bx lr
+;
+; CHECK-V7-LABEL: test4:
+; CHECK-V7: @ %bb.0:
+; CHECK-V7-NEXT: ubfx r0, r0, #8, #8
+; CHECK-V7-NEXT: bx lr
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u
@@ -44,17 +61,19 @@ define zeroext i32 @test4(i32 %A.u) {
}
define zeroext i16 @test5(i32 %A.u) {
- ; CHECK-LABEL: test5
- ; CHECK-V6: uxth
- ; CHECK-V7: uxth
+; CHECK-LABEL: test5:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: bx lr
%B.u = trunc i32 %A.u to i16
ret i16 %B.u
}
define zeroext i32 @test6(i32 %A.u, i32 %B.u) {
- ; CHECK-LABEL: test6
- ; CHECK-V6: uxtah r0, r0, r1
- ; CHECK-V7: uxtah r0, r0, r1
+; CHECK-LABEL: test6:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtah r0, r0, r1
+; CHECK-NEXT: bx lr
%C.u = trunc i32 %B.u to i16
%D.u = zext i16 %C.u to i32
%E.u = add i32 %A.u, %D.u
@@ -62,9 +81,10 @@ define zeroext i32 @test6(i32 %A.u, i32 %B.u) {
}
define zeroext i32 @test7(i32 %A, i32 %X) {
-; CHECK-LABEL: test7
-; CHECK-V6: uxtab r0, r1, r0, ror #8
-; CHECK-V7: uxtab r0, r1, r0, ror #8
+; CHECK-LABEL: test7:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtab r0, r1, r0, ror #8
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
@@ -75,9 +95,10 @@ define zeroext i32 @test7(i32 %A, i32 %X) {
}
define zeroext i32 @test8(i32 %A, i32 %X) {
-; CHECK-LABEL: test8
-; CHECK-V6: uxtab r0, r1, r0, ror #16
-; CHECK-V7: uxtab r0, r1, r0, ror #16
+; CHECK-LABEL: test8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtab r0, r1, r0, ror #16
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 16
%C = shl i32 %A, 16
%D = or i32 %B, %C
@@ -88,9 +109,10 @@ define zeroext i32 @test8(i32 %A, i32 %X) {
}
define zeroext i32 @test9(i32 %A, i32 %X) {
-; CHECK-LABEL: test9
-; CHECK-V6: uxtah r0, r1, r0, ror #8
-; CHECK-V7: uxtah r0, r1, r0, ror #8
+; CHECK-LABEL: test9:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtah r0, r1, r0, ror #8
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
@@ -101,9 +123,10 @@ define zeroext i32 @test9(i32 %A, i32 %X) {
}
define zeroext i32 @test10(i32 %A, i32 %X) {
-; CHECK-LABEL: test10
-; CHECK-V6: uxtah r0, r1, r0, ror #24
-; CHECK-V7: uxtah r0, r1, r0, ror #24
+; CHECK-LABEL: test10:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtah r0, r1, r0, ror #24
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
@@ -114,18 +137,20 @@ define zeroext i32 @test10(i32 %A, i32 %X) {
}
define zeroext i32 @test11(i32 %A, i32 %X) {
-; CHECK-LABEL: test11
-; CHECK-V6: uxtab r0, r1, r0
-; CHECK-V7: uxtab r0, r1, r0
+; CHECK-LABEL: test11:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtab r0, r1, r0
+; CHECK-NEXT: bx lr
%B = and i32 %A, 255
%add = add i32 %X, %B
ret i32 %add
}
define zeroext i32 @test12(i32 %A, i32 %X) {
-; CHECK-LABEL: test12
-; CHECK-V6: uxtab r0, r1, r0, ror #8
-; CHECK-V7: uxtab r0, r1, r0, ror #8
+; CHECK-LABEL: test12:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtab r0, r1, r0, ror #8
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 8
%and = and i32 %B, 255
%add = add i32 %and, %X
@@ -133,9 +158,10 @@ define zeroext i32 @test12(i32 %A, i32 %X) {
}
define zeroext i32 @test13(i32 %A, i32 %X) {
-; CHECK-LABEL: test13
-; CHECK-V6: uxtab r0, r1, r0, ror #16
-; CHECK-V7: uxtab r0, r1, r0, ror #16
+; CHECK-LABEL: test13:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtab r0, r1, r0, ror #16
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 16
%and = and i32 %B, 255
%add = add i32 %and, %X
@@ -143,18 +169,20 @@ define zeroext i32 @test13(i32 %A, i32 %X) {
}
define zeroext i32 @test14(i32 %A, i32 %X) {
-; CHECK-LABEL: test14
-; CHECK-V6: uxtah r0, r1, r0
-; CHECK-V7: uxtah r0, r1, r0
+; CHECK-LABEL: test14:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtah r0, r1, r0
+; CHECK-NEXT: bx lr
%B = and i32 %A, 65535
%add = add i32 %X, %B
ret i32 %add
}
define zeroext i32 @test15(i32 %A, i32 %X) {
-; CHECK-LABEL: test15
-; CHECK-V6: uxtah r0, r1, r0, ror #8
-; CHECK-V7: uxtah r0, r1, r0, ror #8
+; CHECK-LABEL: test15:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtah r0, r1, r0, ror #8
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 8
%and = and i32 %B, 65535
%add = add i32 %and, %X
@@ -162,9 +190,10 @@ define zeroext i32 @test15(i32 %A, i32 %X) {
}
define zeroext i32 @test16(i32 %A, i32 %X) {
-; CHECK-LABEL: test16
-; CHECK-V6: uxtah r0, r1, r0, ror #24
-; CHECK-V7: uxtah r0, r1, r0, ror #24
+; CHECK-LABEL: test16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtah r0, r1, r0, ror #24
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
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