[PATCH] D72187: AMDGPU: Prepare to use scalar register indexing

Mon Jan 20 12:55:01 PST 2020

arsenm marked an inline comment as done.
arsenm added inline comments.

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Comment at: llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir:425
     $m0 = S_MOV_B32 0
-    $sgpr0 = S_MOVRELD_B32 $sgpr0, implicit $m0
+    S_MOVRELD_B32 $sgpr0, $sgpr0, implicit $m0
     S_BRANCH %bb.3
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rampitec wrote:
> It does not define anything. This is not good. It used to define a wrong register though, which is not good either. Can we have a version which will have a whole super reg def and then read the whole super reg as well?
Do you mean just in the test? The way it works here is to keep the instruction definition matching the encoding. The pseudo-expansion adds the implicit use/def of the super register. The alternatives would be to multiply the number of movreld physical instruction definitions 

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  https://reviews.llvm.org/D72187/new/

https://reviews.llvm.org/D72187