[PATCH] D72187: AMDGPU: Prepare to use scalar register indexing

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir:425
     $m0 = S_MOV_B32 0
-    $sgpr0 = S_MOVRELD_B32 $sgpr0, implicit $m0
+    S_MOVRELD_B32 $sgpr0, $sgpr0, implicit $m0
     S_BRANCH %bb.3
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It does not define anything. This is not good. It used to define a wrong register though, which is not good either. Can we have a version which will have a whole super reg def and then read the whole super reg as well?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72187/new/

https://reviews.llvm.org/D72187