[PATCH] D72709: [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.

[Michael Liao via Phabricator via llvm-commits]

hliao added a comment.

yeah, here one example

  //
  //    a: X:sub1 := ..
  //    b: Y      := use(.., X, ..)
  //    c: X:sub0 := ..
  //       .. no use of neither X nor Y ..
  //
  
  when DIE traverses MIR in the reverse order, it won't remove (c) as X is still used by (b). But, when (b) is checked, as Y is not used, it's removed. Then, (a) will be removed since now there's no more use of X. However, after that, only (c) is left. but it is not full definition of X and there's no other definition dominating this def (in fact, a partial def follow a implicit use.)
  
  Even without sub register, similar cases results in the invalid MIR as well, especially considering the PHI node in loop. If you have to DIE in RA phase, you may consider put it before phi-elimination. In general, after DeSSA, only COPYs should be removed and no other should be removed without carefully live range checking.
  
  >>! In D72709#1823444, @uabelho wrote:
  > Hi,
  > 
  > In my out-of-tree target we are running DeadMachineInstructionElim after SSA, and now of course the new assert fails.
  > 
  > But you're saying that it needs SSA or it can cause miscompiles?


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https://reviews.llvm.org/D72709