[PATCH] D68685: [RISCV] Scheduler description for Rocket Core
Shiva Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 13 22:21:09 PST 2020
shiva0217 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVSchedule.td:105
+def ReadIM : SchedRead; // 32 & 64-bit multiply
+def ReadID : SchedRead; // 32 & 64-bit divide
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HsiangKai wrote:
> They are the only two SchedRead definitions. However, there is no place using them. I think you should specify more SchedRead types and associate these SchedRead to input operands in instruction definitions.
Will the SchedRead for input operands be added, so they could be used by ReadAdvance to describe forwarding rules?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D68685/new/
https://reviews.llvm.org/D68685
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