[PATCH] D72627: AMDGPU/GlobalISel: Only map VOP operands to VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 237710.
arsenm added a comment.

Fix a few special cases. I think a few more remain


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72627/new/

https://reviews.llvm.org/D72627

Files:
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

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