[PATCH] D72627: AMDGPU/GlobalISel: Only map VOP operands to VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellar, nhaehnle, kerbowa.
Herald added subscribers: Petar.Avramovic, hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

Previously this was allowing one SGPR in the first source
operand, which technically also avoided violating this for most
operations (but not for special cases reading vcc).

      

This trivially avoids violating the constant bus restriction. We do
need to write some new, smarter operand folds to pick the optimal SGPR
to use in some kind of post-isel fold, but that's purely an
optimization.

      

I was originally thinking we would pick which operands should be SGPRs
in RegBankSelect, but I think this isn't really manageable. There
would be additional complexity to handle every G_* instruction, and
then any nontrivial instruction patterns would need to know when to
avoid violating it, which is likely to be very error prone.

      

I think having all inputs being canonically copies to VGPRs will
simplify the operand folding logic. The current folding we do is
backwards, and only considers one operand at a time, relative to
operands it already has. It therefore poorly handles the case where
there is already a constant bus operand user. If all operands are
copies, it's somewhat simpler to consider all input operands at once
to choose the optimal constant bus user.

     

Since the failure mode for constant bus violations is now a verifier
error and not an selection failure, this moves towards a place where
we can turn on the fallback mode. The SGPR copy folding optimizations
can be left for later.


https://reviews.llvm.org/D72627

Files:
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

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