[PATCH] D72573: [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2870-2871
       Known.One.ashrInPlace(Shift);
     }
     break;
   case ISD::FSHL:
----------------
lebedev.ri wrote:
> Same for signbit given arithmetic right-shift?
ComputeNumSignBits already does something similar for ISA::SRA - it always gets the number of sign bits of Op0 and increases it if the shift amount is constant


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  https://reviews.llvm.org/D72573/new/

https://reviews.llvm.org/D72573