[PATCH] D72573: [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2870-2871
       Known.One.ashrInPlace(Shift);
     }
     break;
   case ISD::FSHL:
----------------
Same for signbit given arithmetic right-shift?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72573/new/

https://reviews.llvm.org/D72573