[llvm] 3772ea9 - [ARM][MVE] Tail predicate VMAX,VMAXA,VMIN,VMINA

[Sam Parker via llvm-commits]

Author: Sam Parker
Date: 2020-01-10T14:24:25Z
New Revision: 3772ea9dd9368cfdc73595854c143bc3f16a5ade

URL: https://github.com/llvm/llvm-project/commit/3772ea9dd9368cfdc73595854c143bc3f16a5ade
DIFF: https://github.com/llvm/llvm-project/commit/3772ea9dd9368cfdc73595854c143bc3f16a5ade.diff

LOG: [ARM][MVE] Tail predicate VMAX,VMAXA,VMIN,VMINA

Add the MVE min and max instructions to our tail predication
whitelist.

Differential Revision: https://reviews.llvm.org/D72502

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrMVE.td
    llvm/unittests/Target/ARM/MachineInstrTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 19dadf229e5a..2b454b4186af 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1138,6 +1138,7 @@ class MVE_VMINMAX<string iname, string suffix, bit U, bits<2> size,
   let Inst{8} = 0b0;
   let Inst{6} = 0b1;
   let Inst{4} = bit_4;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VMINMAX_m<string iname, bit bit_4, MVEVectorVTInfo VTI,
@@ -2298,6 +2299,7 @@ class MVE_VMINMAXA<string iname, string suffix, bits<2> size,
   let Inst{4} = 0b0;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+  let validForTailPredication = 1;
 }
 
 def MVE_VMAXAs8  : MVE_VMINMAXA<"vmaxa", "s8",  0b00, 0b0>;

diff  --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index 581d8be26527..f5b7414decae 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -149,6 +149,24 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VFMA_qr_Sf32:
     case MVE_VFMA_qr_f16:
     case MVE_VFMA_qr_f32:
+    case MVE_VMAXAs16:
+    case MVE_VMAXAs32:
+    case MVE_VMAXAs8:
+    case MVE_VMAXs16:
+    case MVE_VMAXs32:
+    case MVE_VMAXs8:
+    case MVE_VMAXu16:
+    case MVE_VMAXu32:
+    case MVE_VMAXu8:
+    case MVE_VMINAs16:
+    case MVE_VMINAs32:
+    case MVE_VMINAs8:
+    case MVE_VMINs16:
+    case MVE_VMINs32:
+    case MVE_VMINs8:
+    case MVE_VMINu16:
+    case MVE_VMINu32:
+    case MVE_VMINu8:
     case MVE_VMLAS_qr_s16:
     case MVE_VMLAS_qr_s32:
     case MVE_VMLAS_qr_s8: