[PATCH] D72310: [mlir][VectorOps] Implement strided_slice conversion

[River Riddle via Phabricator via llvm-commits]

rriddle requested changes to this revision.
rriddle added inline comments.
This revision now requires changes to proceed.


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Comment at: mlir/include/mlir/IR/Attributes.h:1453
+  using reference = UnderlyingTy;
+  explicit attr_value_iterator(ArrayAttr::iterator it)
+      : llvm::mapped_iterator<ArrayAttr::iterator, UnderlyingTy (*)(Attribute)>(
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This needs more work. Will try to respond by end of day.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D72310/new/

https://reviews.llvm.org/D72310