[llvm] a2d54fc - AMDGPU/GlobalISel: Add some missing G_SELECT testcases
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 7 13:36:43 PST 2020
Author: Matt Arsenault
Date: 2020-01-07T16:36:31-05:00
New Revision: a2d54fc534f7bd3863ca6badb21b3d02a19d6034
URL: https://github.com/llvm/llvm-project/commit/a2d54fc534f7bd3863ca6badb21b3d02a19d6034
DIFF: https://github.com/llvm/llvm-project/commit/a2d54fc534f7bd3863ca6badb21b3d02a19d6034.diff
LOG: AMDGPU/GlobalISel: Add some missing G_SELECT testcases
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
index 71da172e5826..0e3e5ba4ba69 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
@@ -1,6 +1,35 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+---
+name: select_s32_scc
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+
+ ; GCN-LABEL: name: select_s32_scc
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GCN: $scc = COPY [[COPY4]]
+ ; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc
+ ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s32) = COPY $sgpr2
+ %3:sgpr(s32) = COPY $sgpr3
+ %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
+ %5:sgpr(s32) = G_SELECT %4, %2, %3
+ S_ENDPGM 0, implicit %5
+
+...
+
---
name: select_s64_scc
legalized: true
@@ -30,6 +59,65 @@ body: |
...
+---
+name: select_p0_scc
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
+
+ ; GCN-LABEL: name: select_p0_scc
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
+ ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GCN: $scc = COPY [[COPY4]]
+ ; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
+ ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(p0) = COPY $sgpr2_sgpr3
+ %3:sgpr(p0) = COPY $sgpr4_sgpr5
+ %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
+ %5:sgpr(p0) = G_SELECT %4, %2, %3
+ S_ENDPGM 0, implicit %5
+
+...
+
+# FIXME: Handle arbitrary address spaces
+---
+name: select_p1_scc
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
+
+ ; GCN-LABEL: name: select_p1_scc
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
+ ; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
+ ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
+ ; GCN: $scc = COPY [[COPY4]]
+ ; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
+ ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(p1) = COPY $sgpr2_sgpr3
+ %3:sgpr(p1) = COPY $sgpr4_sgpr5
+ %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
+ %5:sgpr(p1) = G_SELECT %4, %2, %3
+ S_ENDPGM 0, implicit %5
+
+...
+
---
name: select_v4s16_scc
legalized: true
@@ -119,6 +207,33 @@ body: |
...
+---
+name: select_s32_vcc
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+ ; GCN-LABEL: name: select_s32_vcc
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY3]], 0, [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; GCN: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = COPY $vgpr3
+ %4:vcc(s1) = G_ICMP intpred(eq), %0, %1
+ %5:vgpr(s32) = G_SELECT %4, %2, %3
+ S_ENDPGM 0, implicit %5
+
+...
+
---
name: select_s16_vcc
legalized: true
@@ -174,3 +289,30 @@ body: |
S_ENDPGM 0, implicit %5
...
+
+---
+name: select_p3_vcc
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+ ; GCN-LABEL: name: select_p3_vcc
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY3]], 0, [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; GCN: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(p3) = COPY $vgpr2
+ %3:vgpr(p3) = COPY $vgpr3
+ %4:vcc(s1) = G_ICMP intpred(eq), %0, %1
+ %5:vgpr(p3) = G_SELECT %4, %2, %3
+ S_ENDPGM 0, implicit %5
+
+...
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