[PATCH] D72302: [X86] Improve lowering of v2i64 sign bit tests on pre-sse4.2 targets

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked 2 inline comments as done.
craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:21579
+        static const int MaskHi[] = { 1, 1, 3, 3 };
+        SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
+
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RKSimon wrote:
> emit PSHUFD directly?
Why? The code below generates 3 regular shuffles just like this.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:21582
+        if (Invert)
+          Result = DAG.getNOT(dl, Result, MVT::v4i32);
+
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RKSimon wrote:
> Would the invert case be better as a PSRAD xmm, 31 + the shuffle ?
I think PSRAD xmm, 31 is equivalent to the non-inverted case. I'm not sure which is better XOR+PCMPGT or PSRAD. There were more execution resources available for pcmpgt then psrad on SSE4.1 era CPU like Penryn. But we might not have handled the XOR in 0 cycles.


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  https://reviews.llvm.org/D72302/new/

https://reviews.llvm.org/D72302