[PATCH] D71934: [AMDGPU] need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict.
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 30 13:48:13 PST 2019
rampitec added inline comments.
================
Comment at: llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll:1
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
+
----------------
Please add -check-prefix=GCN.
================
Comment at: llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll:8
+
+define amdgpu_kernel void @smrd_vmem_war(i32 addrspace(1)* nocapture %0, i64 addrspace(1)* nocapture %1) {
+ %3 = call i32 @llvm.amdgcn.workitem.id.x()
----------------
Test should have no numbered values. Please run opt -instnamer on it.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D71934/new/
https://reviews.llvm.org/D71934
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