[PATCH] D71921: [PowerPC] Use isPredicable bits in instruction definitions

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: hfinkel, kparzysz, PowerPC.
Herald added subscribers: llvm-commits, steven.zhang, shchenz, jsji, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.

Currently, we are using method `isPredicable` to check opcode of machine instr on PowerPC. However, on other platforms, it's adapted to use `isPredicable` bit in instruction themselves. And by default, `TargetInstrInfo::isPredicable(const MachineInstr&)` checks the bit in instr.

This patch only affects opcodes mentioned in current `PPCInstrInfo::isPredicable`, to minimalize changes. We can add it to more opcodes in future patches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71921

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td

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