[PATCH] D66210: [RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa116f28a0d71: [RISCV] Enable the machine outliner for RISC-V (authored by lewis-revill).

Changed prior to commit:
  https://reviews.llvm.org/D66210?vs=234261&id=234732#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/machineoutliner.mir

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