[PATCH] D66210: [RISCV] Enable the machine outliner for RISC-V
Lewis Revill via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 18 09:32:19 PST 2019
lewis-revill added a comment.
In D66210#1787974 <https://reviews.llvm.org/D66210#1787974>, @apazos wrote:
> Can you open a bug for the machine outliner and maybe contact Jessica, may be she can help fix this quickly.
Sorry for the delay. Finding a testcase for X86 is proving extremely time consuming, although I have been able to prove to myself that the same situation is indeed possible. I just don't know enough about the X86 backend to invoke it.
So I think it is easier if I commit the RISC-V implementation, and we can then discuss how to approach the testcase which we already have.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D66210/new/
https://reviews.llvm.org/D66210
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