[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64
Victor Campos via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 18 02:49:19 PST 2019
vhscampos updated this revision to Diff 234493.
vhscampos added a comment.
Changed STOREDUAL instruction selection to use TableGen patterns.
Removed one constraint from LOADDUAL and STOREDUAL.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70072/new/
https://reviews.llvm.org/D70072
Files:
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/CodeGen/ARM/i64_volatile_load_store.ll
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