[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:3549
+    SDValue Ops[] = {SDValue(Pair, 0), Base, RegOffset, ImmOffset, Chain};
+    SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops);
+    ReplaceNode(N, New);
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I think you could implement this pattern in TableGen (grep for REG_SEQUENCE in the ARM .td files).  But probably not the corresponding load pattern, since the inverse opcode doesn't exist, so not a big deal either way.


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Comment at: llvm/lib/Target/ARM/ARMInstrInfo.td:2704
 
+let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1, hasNoSchedulingInfo = 1 in {
+def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr),
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hasExtraDefRegAllocReq shouldn't be necessary; the regular ldrd/strd are weird because the register allocation constraint isn't expressed correctly by the operand types, but you don't have that problem here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072