[PATCH] D71581: [X86] Fix an 8 bit testb being selected when folding a volatile i32 load pattern.

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:5104
+        if (auto *LoadN = dyn_cast<LoadSDNode>(N0.getOperand(0).getNode())) {
+          if (LoadN->isVolatile()) {
+            unsigned NumVolBits = LoadN->getValueType(0).getSizeInBits();
----------------
craig.topper wrote:
> @reames should this be !LoadN->isSimple()?
Yes.

Though, the approach taken with that hit a snag.  I'm probably going to end up reverting a bunch of changes in that whole sequence as I didn't get legalization quite right and have to revisit the design.  It's off in TOT.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71581/new/

https://reviews.llvm.org/D71581