[PATCH] D71581: [X86] Fix an 8 bit testb being selected when folding a volatile i32 load pattern.
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 16 16:34:58 PST 2019
aemerson created this revision.
aemerson added a reviewer: craig.topper.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
We're not allowed to narrow volatile memory accesses.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D71581
Files:
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/test/CodeGen/X86/select-testb-volatile-load.ll
Index: llvm/test/CodeGen/X86/select-testb-volatile-load.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/select-testb-volatile-load.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+
+; This test checks that we don't try to narrow the volatile load by selecting
+; the pattern below into a testb instruction.
+
+define void @testb_volatile(i32 **%ptrptr) {
+; CHECK-LABEL: testb_volatile:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movq (%rdi), %rax
+; CHECK-NEXT: testl $1, (%rax)
+; CHECK-NEXT: jne LBB0_1
+; CHECK-NEXT: ## %bb.2: ## %exit
+; CHECK-NEXT: movl $1, (%rax)
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB0_1: ## %bb2
+; CHECK-NEXT: movl $0, (%rax)
+; CHECK-NEXT: retq
+entry:
+ %ptr = load i32*, i32** %ptrptr, align 8
+ %vol_load = load volatile i32, i32* %ptr, align 4
+ %and = and i32 %vol_load, 1
+ %cmp = icmp eq i32 %and, 0
+ br i1 %cmp, label %exit, label %bb2
+
+bb2:
+ store i32 0, i32 *%ptr, align 4
+ ret void
+
+exit:
+ store i32 1, i32 *%ptr, align 4
+ ret void
+}
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5100,6 +5100,17 @@
MachineSDNode *NewNode;
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
if (tryFoldLoad(Node, N0.getNode(), Reg, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
+ if (auto *LoadN = dyn_cast<LoadSDNode>(N0.getOperand(0).getNode())) {
+ if (LoadN->isVolatile()) {
+ unsigned NumVolBits = LoadN->getValueType(0).getSizeInBits();
+ if (MOpc == X86::TEST8mi && NumVolBits != 8)
+ break;
+ else if (MOpc == X86::TEST16mi && NumVolBits != 16)
+ break;
+ else if (MOpc == X86::TEST32mi && NumVolBits != 32)
+ break;
+ }
+ }
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
Reg.getOperand(0) };
NewNode = CurDAG->getMachineNode(MOpc, dl, MVT::i32, MVT::Other, Ops);
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