[PATCH] D71396: [llvm][NFCi][lMIRVRegNamerUtils] Leverage hash_value for hashing a MachineInstr.

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi marked an inline comment as done.
plotfi added inline comments.


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Comment at: llvm/lib/CodeGen/MIRVRegNamerUtils.cpp:76
+      if (Register::isVirtualRegister(MO.getReg()))
+        return MRI.getVRegDef(MO.getReg())->getOpcode();
+      LLVM_FALLTHROUGH;
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aditya_nandakumar wrote:
> This feels redundant - I wonder if instead of hashing the opcode (which we already do below), we could hash something unique about the definition (Reg Class/Reg Bank/LLT). That way 
> ```
> x(s32), y(s32) = FOO <Ops>
> x(someregclass), y(s64) = FOO <Ops>
> ```
> the above instructions will hash differently.
I think we could hash the regclass/bank along with the opcode. I thought the point of hashing on the opcode directly coming off the def instead of the vreg itself was the main reason the linear hashing technique doesn’t have the ripple effects from previous renaming techniques.

I wonder why the register class isn’t being used for hashing at https://github.com/llvm/llvm-project/blob/6abd01e4624a2c9f8f76e11cc5d57cc7551b5d2a/llvm/lib/CodeGen/MachineOperand.cpp#L347


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https://reviews.llvm.org/D71396