[PATCH] D71396: [llvm][NFCi][lMIRVRegNamerUtils] Leverage hash_value for hashing a MachineInstr.

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar added inline comments.


================
Comment at: llvm/lib/CodeGen/MIRVRegNamerUtils.cpp:76
+      if (Register::isVirtualRegister(MO.getReg()))
+        return MRI.getVRegDef(MO.getReg())->getOpcode();
+      LLVM_FALLTHROUGH;
----------------
This feels redundant - I wonder if instead of hashing the opcode (which we already do below), we could hash something unique about the definition (Reg Class/Reg Bank/LLT). That way 
```
x(s32), y(s32) = FOO <Ops>
x(someregclass), y(s64) = FOO <Ops>
```
the above instructions will hash differently.


Repository:
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  https://reviews.llvm.org/D71396/new/

https://reviews.llvm.org/D71396