[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:10831
+  MRI.setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg);
+  MRI.setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg);
+}
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Oh, I didn't notice this before.

There's a problem here: if we're trying to generate LDRD for the sake of the extra guarantees provided by the some targets, transforming that to LDM is wrong; it doesn't have the same guarantee, and therefore could cause unpredictable, subtle problems.

Probably we want to allocate a GPRPair, instead of allocating two separate registers and trying to tie them together with a hint.  Maybe requires defining a new pseudo-instruction that takes a GPRPair instead of two GPRs.

Or I'd be okay with just restricting the optimization to Thumb2 for now, if you don't want to do the extra work right now.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072