[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Victor Campos via Phabricator via llvm-commits]

vhscampos updated this revision to Diff 233337.
vhscampos added a comment.

1. Update summary to have a better explanation of this patch.
2. Add a post-ISel hook to add register allocation hints to LDRD/STRD operands.
3. In the AArch32 case, move ISel from TableGen back to the C++ side. This is needed because we must have a custom lowering whenever LDRD/STRD selection would normally yield a register offset. The ARM Load/Store Optimizer is not able to handle LDRD/STRD's register offsets in the cases where LDRD/STRD must be reverted to LDM/STM. As such, the C++ instruction selection opts for not generating instructions with a register offset.
4. Improve test by testing several immediate boundary cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072

Files:
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

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