[PATCH] D71298: [AArch64][SVE] Add patterns for scalable vselect

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added a comment.

In D71298#1778345 <https://reviews.llvm.org/D71298#1778345>, @efriedma wrote:

> On a sort of related note, AArch64ISelLowering.cpp says that MVT::nxv1f32 and MVT::nxv1f64 are also legal?  Do we plan to implement isel patterns for them?


`nxv1f16` and `nxv1f64` shouldn't be legal types, that was a mistake on my part
when implementing the initial calling convention for SVE. We avoid `nxv1<eltty>`
types as they can't be split if the element type is too big.  We've also not had
to worry about these types from a vectorization point of view because the
vectorizer normally only generates `VF=1` to indicate it wants to scalarize the
loop and in practice there is little value from vectorization when VF=vscale*1

`MVT::nxv2f16` and `MVT::nxv4f16` are legal types however so maybe it's worth
adding isel patterns for those in this patch?

I'll create a patch to remove `nxv1f16` and `nxv1f64` as legal types.



================
Comment at: llvm/test/CodeGen/AArch64/sve-select.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
----------------
Can this be removed? (I'm not sure if this test was generated?)


================
Comment at: llvm/test/CodeGen/AArch64/sve-select.ll:8-11
+; CHECK-LABEL: sel_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    ret
----------------
nit: can the `CHECK` lines be shifted down a couple of lines to the function body? It would be a little easier to read.


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