[PATCH] D71160: [AArch64][SVE] Implement SPLAT_VECTOR for i1 vectors.
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 6 18:23:45 PST 2019
efriedma created this revision.
efriedma added reviewers: sdesmalen, willlovett, c-rhodes, huntergr.
Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
The generated sequence with whilelo is unintuitive, but it's the best I could come up with given the limited number of SVE instructions that interact with scalar registers. The other sequence I was considering was something like dup+cmpne, but an extra scalar instruction seems better than an extra vector instruction.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D71160
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-vector-splat.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D71160.232682.patch
Type: text/x-patch
Size: 4241 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191207/25b588fe/attachment.bin>
More information about the llvm-commits
mailing list