[PATCH] D71109: [ARM] Disable VLD4 under MVE

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: samparker, SjoerdMeijer, ostannard.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

Alas, using half the available vector registers in a single instruction is just too much for the register allocator to handle. The mve-vldst4.ll test here fails when they are enabled at present. Whilst I look into ways to fix that, this disables the generation of VLD4 by adding a `mve-max-interleave-factor` option, which we currently default to 2.


https://reviews.llvm.org/D71109

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-vld4.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll

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