[PATCH] D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar updated this revision to Diff 232297.
andwar marked an inline comment as done.
andwar added a comment.

- Apply suggestions from @sdesmalen (e.g. add `!Src.hasOneUse()` in `performANDCombine`)
- Removed a bunch of `setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::nxv2i64, Legal)`, which are not needed for this patch
- Simplified `performSignExtendInRegCombine`
- Added patterns for `sext_inreg` (required for the new tests vvvv)
- Added tests that verify that the new DAG Combine rules are not used when the result of gather load has multiple uses


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70812/new/

https://reviews.llvm.org/D70812

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll

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