[PATCH] D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1092
+def int_aarch64_sve_xor         : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_bic_base    : AdvSIMD_2VectorArg_Intrinsic;
+def int_aarch64_sve_bic         : AdvSIMD_Pred2VectorArg_Intrinsic;
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nit: I'd suggest naming this `_unpred` to remove any ambiguity on what `_base` means.


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Comment at: llvm/test/CodeGen/AArch64/sve-pred-log.ll:88
+; CHECK-NEXT: ret
+  %res = call <vscale x 4 x i1> @llvm.aarch64.sve.bic.pred.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
+  ret <vscale x 4 x i1> %res;
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These tests still have `.pred` in the name, but can probably be removed now that these tests have moved to `sve-int-log-pred.ll` ?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70795/new/

https://reviews.llvm.org/D70795