[PATCH] D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr updated this revision to Diff 232182.
dancgr added a comment.

- [AArch64][SVE] Rename intrinsics to re-use logical SVE intrinsics.
- [AArch64][SVE] Change bic instrincis to comply with other predicated instructions
- [AArch64][SVE] Remove trailing backslash from test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70795/new/

https://reviews.llvm.org/D70795

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-int-log-pred.ll
  llvm/test/CodeGen/AArch64/sve-int-log.ll
  llvm/test/CodeGen/AArch64/sve-pred-log.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70795.232182.patch
Type: text/x-patch
Size: 40744 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191204/26f749e6/attachment-0001.bin>