[PATCH] D70881: [X86] Model MXCSR for all AVX512 instructions

Mon Dec 2 17:26:37 PST 2019

pengfei added a comment.

In D70881#1766211 <https://reviews.llvm.org/D70881#1766211>, @craig.topper wrote:

> In D70881#1766203 <https://reviews.llvm.org/D70881#1766203>, @pengfei wrote:
>
> > In D70881#1765349 <https://reviews.llvm.org/D70881#1765349>, @craig.topper wrote:
> >
> > > I think SAE instructions and embedded rounding instructions still read the DAZ and FTZ bits from MXCSR
> >
> >
> > I think so, but currently we don't model DAZ and FTZ, right?
>
>
> The comment in X86RegisterInfo.td says that, but where was that discussed?

You are correct, we do need to model DAZ and FTZ. I think I commented "not modeled" just for simplification. I will commit a patch to model them.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70881/new/

https://reviews.llvm.org/D70881