[PATCH] D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm)

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar created this revision.
andwar added reviewers: sdesmalen, huntergr, kmclaughlin, eli.friedman, rengolin, rovka, dancgr, mgudim.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

This patch adds intrinsics for SVE gather loads from memory addresses generated by a vector base plus immediate index:

- @llvm.aarch64.sve.ld1.gather.imm

This intrinsics maps 1-1 to the corresponding SVE instruction (example for half-words):

- ld1h { z0.d }, p0/z, [z0.d, #16]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70806

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll

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