[PATCH] D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1168
+
+def int_aarch64_sve_ld1_gather_sxtw : Intrinsic<[llvm_anyvector_ty],
+                                                [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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The sxtw/uxtw/uxtw_index/sxtw_index intrinsics all share the same intrinsic signature.
You can create a class for that, and derive from that, similar to what has been done for the other intrinsics.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-unscaled-32bit-offsets.ll:233
+
+; LD1B
+declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8.nxv4i32(<vscale x 4 x i1>, i8*, <vscale x 4 x i32>)
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nit: I don't think these comments add much value here.


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  https://reviews.llvm.org/D70782/new/

https://reviews.llvm.org/D70782