[PATCH] D70666: [WIP][RISCV] Machine Operand Flag Serialization

Tue Nov 26 02:44:21 PST 2019

lenary added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/mir-target-flags.ll:17
+ at g_i = internal global i32 0
+ at t_un = thread_local global i32 42
+ at t_ld = thread_local(localdynamic) global i32 42
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jrtc27 wrote:
> Since these are not external and the file is built without PIC, they are all being optimised to LE. With D70649, making them external would at least make them all IE except for `@t_le`, but in order to get GD and LD you need to have a PIC invocation. This will also get you MO_PLT and MO_GOT_HI cases for free.
Thanks for the help! I have added `external` to all these cases, and `--relocation-model=pic` to the llc invocation, and I think all the flag cases are being hit now.

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Comment at: llvm/test/CodeGen/RISCV/mir-target-flags.ll:64
+  %sum.d = add i32 %sum.c, %d
+  %sum.e = add i32 %sum.b, %e
+  %sum.f = add i32 %sum.e, %f
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jrtc27 wrote:
> RHS typo (hence why there is no `@t_ud` in the test output).
Thanks, fixed!

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70666/new/

https://reviews.llvm.org/D70666