[PATCH] D70614: AMDGPU: Reuse carry out register during FI elimination

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:6216
+  Register UnusedCarry = !RS.isRegUsed(AMDGPU::VCC)
+                             ? AMDGPU::VCC
+                             : RS.scavengeRegister(RI.getBoolRC(), I, 0, false);
----------------
RI.getVCC(), even though right now we cannot hit this with wave32.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1130
+              // Use scavenged unused carry out as offset register.
+              Register ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0);
 
----------------
It ignores wave32 where carry is 32 bit. Granted right now we have no carry adds on all GFX10, but we cannot be sure this will be the same in the future. At least assert if needed the register is 64 bit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70614/new/

https://reviews.llvm.org/D70614