[PATCH] D70401: [RISCV] Implement ilp32e ABI

[Sam Elliott via Phabricator via llvm-commits]

lenary marked 2 inline comments as done.
lenary added a comment.

Some notes and queries about this patch.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2364
     if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
-      assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment");
+      assert(VA.getLocReg() == RISCV::X10 && "Unexpected reg assignment");
       SDValue RetValue2 =
----------------
In the epilog, return values have to be in `a0` and `a1`, which we might as well be explicit about.


================
Comment at: llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll:11
+; This test currently fails because the machine code does not validate:
+; RUN: not llc -mtriple=riscv32 -mattr=+d -target-abi ilp32e -verify-machineinstrs < %s
+; It will need FileCheck %s -check-prefix=ILP32-LP64-NO-D
----------------
@shiva0217 I think this test is failing because of the base pointer patch, but I'm not sure. Can you look at the issue? It thinks that x8 gets killed by a store (which I don't think should be using x8), and therefore x8 is not live when we come to the epilog. It's a super confusing issue.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401