[PATCH] D70400: [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D70400#1750597 <https://reviews.llvm.org/D70400#1750597>, @dp wrote:

> In D70400#1750450 <https://reviews.llvm.org/D70400#1750450>, @rampitec wrote:
>
> > Actually what makes them risky is impuse of M0, so it can be folded around M0 definition. Isn't it cleaner to check for impuse in the SDWA and DPP combiner and disable the combining on these grounds rather than excluding it from codegen completely?
>
>
> Maybe. But I do not understand how codegen can handle these instructions without knowing actual dst and src registers. To support _dpp and _sdwa variants codegen needs the same (or similar) hacks as those implemented for v_movreld_b32.


Hmm. I think you are right:

  v1 = v_and_b32 v2, 0xf
  v3 = v_movrels_b32 v1

Means: v3 = v1[m0], same as v3 = (v1 & 0xf)[m0]
After sdwa conversion it would be: v3 = v2[m0] & 0xf

Not exactly the same thing.


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https://reviews.llvm.org/D70400