[PATCH] D70400: [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

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In D70400#1750450 <https://reviews.llvm.org/D70400#1750450>, @rampitec wrote:

> Actually what makes them risky is impuse of M0, so it can be folded around M0 definition. Isn't it cleaner to check for impuse in the SDWA and DPP combiner and disable the combining on these grounds rather than excluding it from codegen completely?


Maybe. But I do not understand how codegen can handle these instructions without knowing actual dst and src registers. To support _dpp and _sdwa variants codegen needs the same (or similar) hacks as those implemented for v_movreld_b32.


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